1. Technical Field
Exemplary embodiments of the present invention relate to an integrated circuit device, and more particularly, to a semiconductor device and a fabrication method thereof.
2. Related Art
Semiconductor devices need to be more highly integrated, and various studies on the semiconductor devices with high integration and high density have been made.
Even in the phase-change random access memory devices (PCRAMs) that have received attention as memory devices for replacing flash memories, the first priority is to improve integration density. Thus, studies on reduction in a chip area have been increasingly made. However, there are limits to reduce a minimum feature size due to limitation of a light source.
To overcome the limits, a method of fabricating a three-dimensional (3D) PCRAM by fabricating a switching diode in a vertical pillar shape or fabricating a switching transistor using a vertical pillar and a vertical gate, is suggested. However, there are difficulties in fabricating the vertical pillar of the 3D PCRAM. In particular, a height of the vertical pillar needs to be increased to improve off current characteristics of a switching diode using the vertical pillar. However, an aspect ratio is increased due to the increase in the height of the vertical pillar, which creates difficulties in the process and causes diode leaning. Further, the height of the vertical pillar needs to be increased to ensure an effective channel length even in a switching transistor using the vertical pillar. In the switching transistor, similar to the switching diode described above, an aspect ratio is also increased due to the increase in the height of the vertical pillar, which creates difficulties in the process and causes leaning.
A switching device having a horizontal channel structure is suggested to overcome the limits of the vertical switching device,
FIGS. 1 and 2A to 2C are views illustrating a structure of a general switching device having a horizontal channel structure.
FIG. 1 is a perspective view of a part of a general switching device 10 having a horizontal channel structure. FIG. 2A is a side view of the part shown in FIG. 1 when viewed in an X-direction. FIG. 2B is a cross-sectional view of the part taken along line X11-X12 of FIG. 1. FIG. 2C is a side view of the part shown in FIG. 1 when viewed in a Y-direction.
An active region 105 is formed on a semiconductor substrate 101 in which a common source region (not shown) is formed. The active region 105 may be a line pattern extending to a first direction. A predetermined portion of the active region 105 is connected to the semiconductor substrate 101, and a remaining portion of the active region 105 is insulated from the semiconductor substrate 101 by an insulating layer 103. The remaining portion of the active region 105 disposed on the insulating layer 103 serves as a drain region D, and the predetermined portion of the active region 105 connected to the common source region serves as a source region S.
A gate structure 107, extending to a second direction perpendicular to the first direction and surrounding a side and an upper surface of the active region 105, is formed on the active region 105. The gate structures 107 having a line shape are formed on the drain region D in a predetermined interval. A spacer 109 is formed on the source region S between the gate structures 107 and on sidewalls of the gate structures 107. A space between the gate structures 107 is buried with an interlayer insulating layer 111.
In the switching device 107 having the horizontal channel structure, the gate structure 107 is formed to have a stacking structure of a gate insulating layer 1071, a gate conductive layer 1073, a barrier metal layer 1075, and a hard mask layer 1077. The gate conductive layer 1073 may be a polysilicon layer doped with impurities, the barrier metal layer 1075 may be a tungsten (W) layer, and the hard mask layer 1077 may be a silicon nitride layer.
That is, in the general switching device having the horizontal channel structure, a gate electrode (a word line) is formed of a polysilicon layer and a W layer. A height of the gate structure 107 is increased by the gate electrode, and thus an aspect ratio increases accordingly. The increase in the aspect ratio causes leaning during an etching and cleaning process for gate formation, and the gate structure may be collapsed. Therefore, fabrication yield may be reduced.